1. Field of the Disclosure
Embodiments of the present disclosure relate to a method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus.
2. Description of the Related Art
Integrated circuits (IC) may need to communicate with other ICs or modules in any given system design. The ever increasing processing and computation speed of ICs has created a growing demand for high-bandwidth input and output (IO) on these ICs, which is achieved by increasing the signaling rate of each IO pin as well as increasing the number of IO pins on the chip. While some internal circuits can operate at 10's of Gbps, the performance of the link is limited by the characteristics of the channel, namely, the electrical path from one IC die to the other. In order to achieve desired data rates over existing channels, many multi-Gbps links use complex signal processing to overcome the channel limitations. One such example for improving performance of IOs is to change the signaling method and the channel media by using high speed serializer/deserializer (SERDES) link. These circuits convert data between serial data and parallel interfaces in each direction.
Implementations of SERDES are sometimes combined with implementations of encoding/decoding circuits. The purpose of encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier clock recovery in the receiver, to provide framing, and to provide DC balance. A common coding scheme used with SERDES is 8B/10B encoding. This supports DC-balance, provides framing, and guarantees transitions. The guaranteed transitions allow a receiver to extract the embedded clock. The control codes allow framing, typically on the start of a packet. The 8B/10B SERDES parallel side interfaces may have 1 clock line, 1 control line and 8 data lines, however it may have the clock and control lines integrated in the data lines. Another common coding scheme used with SERDES is 64B/66B encoding. This scheme statistically delivers DC-balance and transitions. Framing is delivered through the deterministic transitions of the added framing bits. Also, SERDES can be implemented in combination with pseudo-random binary sequence (PRBS) scrambling data. There exist a number of other coding schemes that could also be used to implement SERDES that provide the necessary transitions for clock extraction.
A CDR circuit is used to align sampling clock at the receiver with incoming data adaptively and is critical for high speed SERDES link. Working with a received signal can pose the issues of clock recovery and optimum phase selection. Clock recovery is the process of synchronizing a receiver clock with the transmitter clock used when the signal was generated. Phase selection is the process of selecting a phase with respect to the receiver clock at which to sample the received signal. Such a phase selection is acceptable when it provides a good signal-to-noise ratio (SNR) for accurate data recovery from the received signal. The process of clock recovery, and sometimes phase selection as well, is called clock and data recovery. The concerns that are raised are those of area, power, and latency of the implemented CDR.
Many clock and data recovery schemes today use a phase lock loop (PLL). This method is costly both in area and power because PLLs are known to consume a relatively large amount depending on the application. Another method of CDR is 2×-oversampling the data. When data rates are slower (less than 5 or 6 Gbps), a popular choice of CDR is bang-bang CDR, which relies on 2×-oversampling of the incoming data.
Another algorithm for timing extraction is called the Mueller-Muller (MM) algorithm which was first described in a journal article in 1975. The MM-algorithm is a method for generating a timing error signal H(-1) (also called a timing error detector). The MM algorithm only requires one sample per symbol and has been implemented in some applications for long distance telecom.
CDR methods would benefit from having a high bandwidth. Specifically, a high bandwidth allows for tracking and filtering of higher frequency jitters, both deterministic jitter and lower frequency phase noise of random noise jitter in the distributed and multiplied reference block. Deterministic jitter is a type of data signal or clock timing jitter that is predictable and therefore reproducible. Periodic jitter, data-dependent jitter, and duty-cycle dependent jitter are all types of deterministic jitter. Random noise jitter, also called Gaussian jitter, is unpredictable electronic timing noise. Jitter is important to one of ordinary skill in the art due to the trend of increasing clock frequencies in digital electronic circuitry. Higher clock frequencies have smaller eye openings, and thus impose tighter tolerances on jitter.
On the other hand, a desirable trait of a lower bandwidth CDR is the ability to have a low CDR jitter as compared to a higher bandwidth CDR. What provides for this is the ability of the recovered clock phase to move very sluggishly in response to changes in the signal. The recovered clock phase wants to find the average point between all zero crossings. A perfect CDR, from the data dependent jitter (DDJ) data eye opening sense, would lock to the center of an eye diagram and never move. Current standards specify very high CDR bandwidths that can be challenging because they lead to higher DDJ induced by CDR jitter. High orders of averaging, such as up/down threshold counter CDR, is relatively simple to implement and may provide an additional level of complexity to jitter reduction.
Overall, a mix of attributes are desirable. Namely, a high CDR bandwidth (e.g. Fbaud/1667) to meet the small signal response of standards like IEEE 802.3ap. Additionally, not allowing such a high bandwidth, and therefore an inherently jittery, CDR to track DDJ created by data zero crossings that are near the extremes of the zero crossing probability density function (pdf). This may be beneficial because the CDR would likely not respond as strongly to zero crossings that may move the recovered clock phase quickly from its desired nominal position at the mean between all data zero crossings.